Semiconductor manufacturing and packaging technology has evolved to the point where device packages can include multiple integrated circuit chips that are bonded together in a stacked, three-dimensional relationship. Such packages provide a smaller form factor and higher integration density at the package level. The chip stack configuration is amenable to high-speed operation, higher fan-out of signals, reduced noise levels for signal transmission between chips, low power operation, and enhanced functionality within a single package.
Three-dimensional bonding technology continues to progress. In a package level bonding configuration, devices are formed on a semiconductor wafer, and diced into chips. The individual chips are packaged in separate packages, and the packages are stacked and bonded together to form a multiple stack package (MSP). The resulting MSPs enjoyed widespread use in the past, but are relatively bulky and cumbersome for modem applications.
In a chip level bonding configuration, devices are formed on a semiconductor wafer, and diced into chips. The individual chips are stacked and bonded, and the chip stack is packaged within a single, common, package to form a multiple chip package (MCP) or a three-dimensional chip stack package (CSP). The resulting MCPs have characteristically high yield, however, process throughput is a problem, as each individual chip needs to be handled during alignment and bonding processes.
Recently, wafer level bonding configurations have become popular. In a wafer level bonding configuration, devices are formed on a semiconductor wafer, and multiple wafers are stacked so that their corresponding chips are aligned. The wafer stack is bonded together, and then diced into chip stacks. The chip stacks are each packaged within a single, common, package to form a wafer-level three-dimensional chip stack package (WL CSP). The resulting WL CSPs suffer from low yield. However, process throughput is high, as handling of each individual chip is not required, since the chips are stacked at the wafer level.
Chip level bonding and wafer level bonding are generally complicated and unstable manufacturing processes. In such bonding approaches, the individual chips transfer signals to each other in a vertical direction using inter-chip, vertical vias. The inter-chip vias pass through the respective chip substrates, and include a landing pad feature at a top portion thereof and a bump feature at a bottom portion thereof. When a bump of one chip is bonded with a pad of another chip according to the conventional approach, electrical bonding of the bump and pad first takes place for example using a thermo-compression process at a temperature at least equal to the bonding eutectic point of the metals employed at the junction, and is followed by an underfill injection process for filling the gap between the chip substrates to secure mechanical bonding. The underfill process is unreliable, since the gap between the lower and upper chip substrates is small, for example on the order of 20 μm. If the underfill process does not result in a complete and uniform fill of the gap, then any resulting voids can increase the likelihood of future generation of cracks. Such cracks can propagate during future heating and cooling cycles, decreasing the reliability of the resulting chip stack device.
In addition, mechanical stress can develop between layers of a chip or between-adjacent chips of a package. Such stress is typically caused by a mismatch in coefficient of thermal expansion (CTE) between two adjacent layers. In the above chip stack configuration, the chip substrate, the metal of the landing pad, and the bonding material all have different CTE values. Such CTE mismatch can cause further cracking and delamination when subjected to numerous heating and cooling thermal cycles, negatively affecting device yield during manufacture, and device reliability during operation.